Semiconductor devices contain transistor elements and conductive lines of metal integrated with one another on a semiconductor substrate. In terms of location, the transistor elements are at the bottom of the device, so that they may be in direct contact with the underlying semiconductor substrate. Metal contacts electrically couple the transistor elements with the first level of metallization. Metal vias electrically couple the metal layers to one another. A dielectric thin film insulates the metal layers. The insulator exists between metallization layers, as well as surrounding the contacts and vias.
A semiconductor device is manufactured sequentially where one film is fabricated at a time. The sequence generally includes depositing a thin film material, patterning the material using photolithography and plasma etching, and then depositing another thin film material on the patterned material. There may be planarization steps in between the deposition steps, to reduce topographical effects that can limit photolithography and etching.
The metallization sequence of fabrication is usually as follows. A layer of silicon oxide is deposited on the substrate. The substrate may be the transistor elements or an underlying layer of metallization. Openings are formed in the silicon oxide. These openings are usually shaped as holes. The openings are filled with a conductor metal, usually aluminum or tungsten to form contacts or vias, as the case may be. Excess metal is removed from the surface and the surface is planarized. Then, a metallization material is deposited on the planarized silicon oxide containing contact or via plugs, usually this is aluminum. The aluminum is patterned using plasma etching to form electrically conductive lines that are coupled to the underlying metal or transistor elements through vias or contacts. Then, the patterned aluminum lines are covered with silicon oxide. Then, openings are formed in the silicon oxide, and the openings are filled with metal to create vias. The sequence is repeated until the desired number of metallization layers is attained.
In a semiconductor manufacturing method known as "damascene", a layer of silicon oxide is deposited on a substrate surface, and openings are formed in the silicon oxide to create a trench pattern in the shape of metal lines. Then, metal is deposited into the trenches of the pattern. The metal may be planarized to remove excess from the top surface of the silicon oxide. The result is a series of metal lines surrounded by silicon oxide, but it is achieved by depositing the metal into trenches in the silicon oxide, as opposed to depositing a blanket layer of metal and patterning it to form lines.
As the trend in semiconductor fabrication moves toward using copper as the conductive metal, it is desirable to use damascene, which avoids etching metal, because of technical problems with plasma etching copper. A limitation to the damascene process, however, is that it is difficult to properly endpoint the silicon oxide etch. This is because, the silicon oxide not only serves as the filler material around the metal lines, it also serves as insulation between metallization layers. Thus, a portion of the silicon oxide resides below the level on which to place the metal lines. It is evident, then, that when the silicon oxide must be etched, endpointing is difficult because it must be etched to enough depth to expose underlying vias, but in places where there are no vias to expose, the etch simply must be stopped to a measured depth. Simply stopping an etch to a measured depth can be done at a designated point on a substrate, but difficulties arise when the etch stop must be done uniformly across the substrate.
To address the etch stop problem with damascene, it is desirable to utilize an etch stop film, so that when the etch stop film is reached, the selectivity of the etch process favoring the silicon oxide will enable etch endpointing to be done more uniformly across the substrate. The etch stop film must also have insulative properties. A proposed etch stop film is silicon nitride.
Silicon nitride and silicon oxide are both formed using chemical vapor deposition. Each is traditionally formed in separate processing chambers. A sequence for forming the films may be to insert a substrate into a silicon nitride process chamber, deposit the silicon nitride, remove the substrate, insert the substrate into a silicon oxide chamber, and form the silicon oxide. There is an obvious downside to using two separate chambers which is that, when the substrate is removed from the silicon nitride process chamber, contamination could form on the film. The contamination could inhibit the formation of chemical bonds and result in adhesion problems when the silicon oxide is formed on the silicon nitride. Another problem with using two separate processing chambers is simply added process time from maneuvering the substrate from one processing chamber to another. Another problem with using silicon nitride and silicon oxide as a stack is the abruptness of the nitrogen content and oxygen content of the films at the film interface. An abrupt interface leads to adhesion problems for the silicon oxide due to large interfacial stresses.
It would be advantageous to avoid the contamination, extra processing time, and adhesion problems when utilizing a stacked dielectric film of silicon nitride and silicon oxide as the insulator in semiconductor devices.